MC3S12RG128 Datasheet, PDF (289/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Module Base + 0x000A
R
W
Reset
7
EDG7B
0
6
EDG7A
0
5
EDG6B
0
4
EDG6A
0
3
EDG5B
0
2
EDG5A
0
1
EDG4B
0
0
EDG4A
0
Module Base + 0x000B
R
W
Reset
7
EDG3B
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
1
EDG0B
0
0
0
0
0
0
0
Figure 10-11. Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
0
EDG0A
0
Read or write anytime.
Table 10-7. TCTL3/TCTL4 Field Descriptions
Field
Description
7–0
EDG[7:0]B
EDG[7:0]A
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
The four pairs of control bits of TCTL4 also configure the 8 bit pulse accumulators PAC0–PAC3.
For 16-bit pulse accumulator PACB, EDGE0B, and EDGE0A, control bits of TCTL4 will decide the active edge.
See Table 10-8.
.
Table 10-8. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
289