MC3S12RG128 Datasheet, PDF (20/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
— Programmable rising and falling edge trigger
• Memory Options:
— 128K Byte or 64K Byte ROM
— 8K Byte RAM
• Two 8-channel Analog-to-Digital Converters
— 10-bit resolution
— External conversion trigger capability
• Two 1M bit per second, CAN 2.0 A, B software compatible modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
— Four separate interrupt channels for Rx, Tx, error and wake-up
— Low-pass filter wake-up function
— Loop-back for self test operation
• Enhanced Capture Timer
— 16-bit main counter with 7-bit prescaler
— 8 programmable input capture or output compare channels
— Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
— Programmable period and duty cycle
— 8-bit 8-channel or 16-bit 4-channel
— Separate control for each pulse width and duty cycle
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
— Fast emergency shutdown input
— Usable as interrupt inputs
• Serial interfaces
— Two asynchronous Serial Communications Interfaces (SCI)
— Two Synchronous Serial Peripheral Interface (SPI)
• Inter-IC Bus (IIC)
— Compatible with I²C Bus standard
— Multi-master operation
— Software programmable for one of 256 different serial clock frequencies
• Internal 2.5V Regulator
— Supports an input voltage range from 2.97V to 5.5V
— Low power mode capability
— Includes low voltage reset (LVR) circuitry
— Includes low voltage interrupt (LVI) circuitry
• 112-Pin LQFP and 80-Pin QFP package options
— I/O lines with 5V input and drive capability
MC3S12RG128 Data Sheet, Rev. 1.05
20
Freescale Semiconductor