MC3S12RG128 Datasheet, PDF (454/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4 Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the
design from the end user perspective in a number of subsections.
Figure 16-9 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial
communication between the CPU and remote devices, including other CPUs. The SCI transmitter and
receiver operate independently, although they use the same baud rate generator. The CPU monitors the
status of the SCI, writes the data to be transmitted, and processes received data.
RXD
SBR12–SBR0
BUS
CLOCK
BAUD RATE
GENERATOR
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
RECEIVE
AND WAKEUP
CONTROL
DATA FORMAT
CONTROL
÷16
TRANSMIT
CONTROL
T8
TRANSMIT
SHIFT REGISTER
RE
RWU
LOOPS
RSRC
M
WAKE
ILT
PE
PT
TE
LOOPS
SBK
RSRC
R8
NF
FE
PF
RAF
ILIE
IDLE
RDRF
OR
RIE
TIE
TDRE
TC
TCIE
IRQ
TO CPU
SCI DATA
REGISTER
TXD
Figure 16-9. SCI Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05
454
Freescale Semiconductor