MC3S12RG128 Datasheet, PDF (290/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 10-12. Timer Interrupt Enable Register (TIE)
Read or write anytime.
Field
7–0
C[7:0]I
Table 10-9. TIE Field Descriptions
Description
Input Capture/Output Compare “n” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
MC3S12RG128 Data Sheet, Rev. 1.05
290
Freescale Semiconductor