MC3S12RG128 Datasheet, PDF (517/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

2 _{At those low power dissipation levels TJ = TA can be assumed}
Appendix A Electrical Characteristics
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD
accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
A.2.1 ATD Operating Characteristics In 5V Range
The Table A-9 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-9. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= V_DDA <=5V+10%
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reference Potential
2
C Differential Reference Voltage¹
Low
V_RL
High
V_RH
V_SSA
V_DDA/2
V_DDA/2
V
V_DDA
V
V_RH-V_RL
4.50
5.00
5.50
V
3 D ATD Clock Frequency
f_ATDCLK
0.5
2.0
MHz
4 D ATD 10-Bit Conversion Period
Clock Cycles² N_CONV10
14
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV10
7
28
Cycles
14
µs
5 D ATD 8-Bit Conversion Period
Clock Cycles N_CONV10
12
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV10
6
26
Cycles
13
µs
6
D Recovery Time (V_DDA=5.0 Volts)
t_REC
20
µs
7
P Reference Supply current
I_REF
0.375³
mA
1 _{Full accuracy is not guaranteed when differential voltage is less than 4.75V}
2 _{The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample}
period of 16 ATD clocks.
3 _{This applies per ATD module, i.e. for 2 ATD modules this number is doubled.}
A.2.2 ATD Operating Characteristics In 3.3V Range
The Table A-10 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
517