MC3S12RG128 Datasheet, PDF (66/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
1.4.1.1 Securing the Microcontroller
The status of security of the part is determined by the security bits located in the ROM module. These
non-volatile bits will keep the part secured through resetting the part and through powering down the part.
The security byte resides in a portion of the ROM array.
Check the ROM Block User Guide for more details on the security configuration.
1.4.1.2 Operation of the Secured Microcontroller
1.4.1.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
1.4.1.2.2 Executing from External Memory
Disabling the internal ROM will unsecure the microcontroller and will also unblock the BDM. As a
consequence, executing from external space with a secured microcontroller is not possible. Please note that
in the 80 pin package the ROMCTL pin is not accessable externally but is pulled to ‘1’ internally by a
pull-up resistor.
1.4.1.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal ROM must be disabled. This can be done by selecting
expanded mode or by starting in special single chip mode. Unsecuring is also possible via the Backdoor
Key Access. Refer to ROM Block Guide for details.
If a secure part is reset to special single chip mode, BDM firmware will disable the ROM by clearing the
ROMON bit (Bit0 in the MISC register). The BDM software commands are unblocked and the part can be
used in unsecure mode. In this state (secured ROM disabled, part unsecured) setting the ROMON bit again
has no effect on the memory map, i.e. ROM remains disabled until next reset.
1.5 Modes of Operation
1.5.1 User Modes
1.5.1.1 Normal Expanded Wide Mode
Ports A, B and K are configured as a 23-bit address bus during the address phase, port A and B are
configured as 16-bit data bus during the data-phase, and port E provides bus control and status signals. This
mode allows 16-bit external memory and peripheral devices to be interfaced to the system.
MC3S12RG128 Data Sheet, Rev. 1.05
66
Freescale Semiconductor