MC3S12RG128 Datasheet, PDF (300/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.20 16-Bit Modulus Down-Counter Flag Register (MCFLG)
Module Base + 0x0027
R
W
Reset
7
6
5
4
3
2
1
0
0
0
POLF3
POLF2
POLF1
MCZF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-24. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write: Only for clearing bit 7
Table 10-20. MCFLG Field Descriptions
0
POLF0
0
Field
Description
7
MCZF
Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000. A write
one to this bit clears the flag. Write zero has no effect. Any access to the MCCNT register will clear the MCZF
flag in this register when TFFCA bit in register TSCR(0x0006) is set.
3–0
POLF[3:0]
First Input Capture Polarity Status — This are read only bits. Write to these bits has no effect. Each status bit
gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read.
Each POLFn corresponds to a timer PORTn input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.
MC3S12RG128 Data Sheet, Rev. 1.05
300
Freescale Semiconductor