MC3S12RG128 Datasheet, PDF (98/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.8 Port P Interrupt Flag Register (PIFP)
Module Base + 0x_001F
R
W
Reset
7
PIFP7
0
6
PIFP6
0
5
PIFP5
0
4
PIFP4
0
3
PIFP3
0
2
PIFP2
0
1
PIFP1
0
0
PIFP0
0
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSP register. To clear this flag, write “1” to the corresponding bit in the PIFP register.
Writing a “0” has no effect.
Table 2-28. Field PIFP Descriptions
Field
Description
7–0
PIFP[7:0]
Interrupt Flags Port P Bits
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
2.3.2.6 Port H Registers
2.3.2.6.1 Port H I/O Register (PTH)
Module Base + 0x_0020
R
W
SPI
Reset
7
PTH7
SS2
0
6
PTH6
SCK2
0
5
PTH5
4
PTH4
3
PTH3
2
PTH2
MOSI2
MISO2
SS1
SCK1
0
0
0
0
Figure 2-32. Port H I/O Register (PTH)
1
PTH1
MOSI1
0
0
PTH0
MISO1
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read. The SPI function takes precedence over the general purpose I/O
function associated with if enabled. Refer to SPI Block Guide for details.
MC3S12RG128 Data Sheet, Rev. 1.05
98
Freescale Semiconductor