MC3S12RG128 Datasheet, PDF (367/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Module Base + 0x0018 (CANIDAR4)
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 12-20. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AC[7:0]
Table 12-20. CANIDAR4–CANIDAR7 Register Field Descriptions
Description
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
367