MC3S12RG128 Datasheet, PDF (245/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Register
Name
0x0005
CLKSEL
0x0006
PLLCTL
0x0007
RTICTL
0x0008
COPCTL
0x0009
FORBYP
0x000A
CTCTL
0x000B
ARMCOP
Bit 7
6
5
4
3
2
R
PLLSEL
W
PSTP SYSWAI ROAWAI PLLWAI
CWAI
R
0
CME
PLLON AUTO
ACQ
PRE
W
R
0
W
RTR6
RTR5
RTR4
RTR3
RTR2
R
0
0
0
WCOP RSBCK
CR2
W
R
0
0
0
0
0
0
W
R
0
0
0
0
0
0
W
R
0
W Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary (continued)
1
Bit 0
RTIWAI COPWAI
PCE
SCME
RTR1
RTR0
CR1
0
0
CR0
0
0
0
Bit 1
0
Bit 0
9.3.1.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f_SCM).
PLLCLK = 2xOSCCLKx₍---⁽_R--^S--_E-^Y---_F-^N--_D---^R--_V----⁺--₊--¹---₁-⁾--₎
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Module Base + 0x0000
7
R
0
W
6
5
4
3
2
0
SYN5
SYNR
SYN3
SYN2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-4. CRG Synthesizer Register (SYNR)
1
SYN1
0
0
SYN0
0
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
245