MC3S12RG128 Datasheet, PDF (244/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
V_DDPLL
MCU
CS
CP
RS
XFC
Figure 9-2. PLL Loop Filter Connections
9.2.3 RESET — Reset Pin
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
9.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRG.
9.3.1 Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register
Name
0x0000
SYNR
0x0001
REFDV
0x0002
CTFLG
0x0003
CRGFLG
0x0004
CRGINT
Bit 7
R
0
W
R
0
W
R
0
W
R
RTIF
W
R
RTIE
W
6
5
4
3
2
1
Bit 0
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0
0
0
REFDV3 REFDV2 REFDV1 REFDV0
0
0
0
0
0
0
0
PORF
0
LVRF
LOCKIF
LOCK
TRACK
SCMIF
0
0
LOCKIE
0
SCMIE
SCM
0
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05
244
Freescale Semiconductor