MC3S12RG128 Datasheet, PDF (68/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
1.5.2.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
1.5.2.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
To further reduce the power consumption the peripherals can turn off their local clocks individually.
1.5.2.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
1.6 Resets and Interrupts
Consult the Exception Processing section of the S12 CPU Reference Manual for information on resets and
interrupts.
1.6.1 Vectors
Table 1-9 lists interrupt sources and vectors in default order of priority.
Table 1-9. Interrupt Vector Locations
Vector Address
0xFFFE, 0xFFFF
0xFFFC, 0xFFFD
0xFFFA, 0xFFFB
0xFFF8, 0xFFF9
0xFFF6, 0xFFF7
0xFFF4, 0xFFF5
0xFFF2, 0xFFF3
0xFFF0, 0xFFF1
0xFFEE, 0xFFEF
0xFFEC, 0xFFED
0xFFEA, 0xFFEB
0xFFE8, 0xFFE9
0xFFE6, 0xFFE7
0xFFE4, 0xFFE5
0xFFE2, 0xFFE3
0xFFE0, 0xFFE1
0xFFDE, 0xFFDF
Interrupt Source
Reset
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real Time Interrupt
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
CCR
Mask
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
Local Enable
None
COPCTL (CME, FCME)
COP rate select
None
None
None
INTCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOF)
HPRIO Value
to Elevate
–
–
–
–
–
–
0xF2
0xF0
0xEE
0xEC
0xEA
0xE8
0xE6
0xE4
0xE2
0xE0
0xDE
MC3S12RG128 Data Sheet, Rev. 1.05
68
Freescale Semiconductor