MC3S12RG128 Datasheet, PDF (95/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.2.5.2
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Port P Input Register (PTIP)
Module Base + 0x_0019
R
W
Reset
7
PTIP7
—
Read: Anytime.
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-25. Port P Input Register (PTIP)
1
PTIP1
—
0
PTIP0
—
Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can be also used to detect overload
or short circuit conditions on output pins.
2.3.2.5.3 Port P Data Direction Register (DDRP)
Module Base + 0x_001A
7
R
DDRP7
W
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
1
DDRP1
0
DDRP0
Reset
0
0
0
0
0
0
0
0
Read: Anytime.
Figure 2-26. Port P Data Direction Register (DDRP)
Write: Anytime.
This register configures each port P pin as either input or output.
• If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
• The PWM forces the I/O state to be an output for each port line associated with an enabled
PWM7-0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled.
• If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI Block Guide for
details.
• The DDRM bits revert to controlling the I/O direction of a pin when the associated PWM channel
is disabled.
Table 2-23. DDRP Field Descriptions
Field
Description
7–0
DDRP[7:0]
Data Direction Port P Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP
or PTIP registers, when changing the DDRP register.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
95