MC3S12RG128 Datasheet, PDF (107/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.7 Port J Interrupt Enable Register (PIEJ)
Module Base + 0x_002E
7
6
5
4
3
2
1
0
R
0
0
0
0
PIEJ7
PIEJ6
PIEJ1
PIEJ0
W
Reset
0
0
—
—
—
—
0
0
= Unimplemented or Reserved
Read: Anytime.
Figure 2-46. Port J Interrupt Enable Register (PIEJ)
Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port J.
Table 2-40. PIEJ Field Descriptions
Field
Description
7, 6, 1, 0
PIEJ[7:6]
PIEJ]1:0]
Interrupt Enable Port J Bits
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
2.3.2.7.8 Port J Interrupt Flag Register (PIFJ)
Module Base + 0x_002F
7
6
5
4
3
2
1
0
R
0
0
0
0
PIFJ7
PIFJ6
PIFJ1
PIFJ0
W
Reset
0
0
—
—
—
—
0
0
= Unimplemented or Reserved
Read: Anytime.
Figure 2-47. Port J Interrupt Flag Register (PIFJ)
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in the PIFJ register.
Writing a “0” has no effect.
Table 2-41. PIFJ Field Descriptions
Field
Description
7, 6, 1, 0
PIFJ[7:6]
PIFJ[1:0]
Interrupt Flags Port J Bits
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
107