MC3S12RG128 Datasheet, PDF (211/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Breakpoint Module (BKPV1) Block Description
7.4 Functional Description
The Breakpoint sub-block supports two modes of operation: Dual Address Mode and Full Breakpoint
Mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints
occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just
before a specific instruction executes. The action taken upon a successful match can be to either place the
CPU in Background Debug Mode or to initiate a software interrupt.
7.4.1 Modes of Operation
The Breakpoint can operate in Dual Address Mode or Full Breakpoint Mode. Each of these modes is
discussed in the subsections below.
7.4.1.1 Dual Address Mode
When Dual Address Mode is enabled, two address breakpoints can be set. Each breakpoint can cause the
system to enter Background Debug Mode or to initiate a software interrupt based upon the state of the
BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a
higher priority than SWI requests. No data breakpoints are allowed in this mode.
The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. The
BKxMBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly or is a
range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes,
and/or memory expansion. The BKxRW and BKxRWE bits in the BKPCT1 register select whether the
type of bus cycle to match is a read, write, or both when performing forced breakpoints.
7.4.1.2 Full Breakpoint Mode
Full Breakpoint Mode requires a match on address and data for a breakpoint to occur. Upon a successful
match, the system will enter Background Debug Mode or initiate a software interrupt based upon the state
of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have
a higher priority than SWI requests. R/W matches are also allowed in this mode.
The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. If the
BKTAG bit is set in BKPCT0, then only address is matched, and data is ignored. The BK0MBH:L bits in
the BKPCT1 register select whether or not the breakpoint is matched exactly, is a range breakpoint, or is
in page space. The BK1MBH:L bits in the BKPCT1 register select whether the data is matched on the high
byte, low byte, or both bytes. The BK0RW and BK0RWE bits in the BKPCT1 register select whether the
type of bus cycle to match is a read or a write when performing forced breakpoints. BK1RW and BK1RWE
bits in the BKPCT1 register are not used in Full Breakpoint Mode.
7.4.2 Breakpoint Priority
Breakpoint operation is first determined by the state of BDM. If BDM is already active, meaning the CPU
is executing out of BDM firmware, Breakpoints are not allowed. In addition, while in BDM trace mode,
tagging into BDM is not allowed. If BDM is not active, the Breakpoint will give priority to BDM requests
over SWI requests. This condition applies to both forced and tagged breakpoints.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
211