MC3S12RG128 Datasheet, PDF (119/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

3.3.1.4
Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-4. External Stretch Bit Definition
Stretch Bit EXSTR1
0
0
1
1
Stretch Bit EXSTR0
0
1
0
1
Number of E Clocks Stretched
0
1
2
3
Reserved Test Register 0 (MTST0)
Module Base + 0x0014
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-6. Reserved Test Register 0 (MTST0)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
3.3.1.5 Reserved Test Register 1 (MTST1)
Module Base + 0x0017
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 3-7. Reserved Test Register 1 (MTST1)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
119