MC3S12RG128 Datasheet, PDF (116/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.1 Initialization of Internal RAM Position Register (INITRM)
Module Base + 0x0010
Starting address location affected by INITRG register setting.
R
W
Reset
7
6
5
4
3
2
1
0
0
RAM15
RAM14
RAM13
RAM12
RAM11
0
0
0
0
1
0
0
= Unimplemented or Reserved
Figure 3-3. Initialization of Internal RAM Position Register (INITRM)
0
RAMHAL
1
Read: Anytime
Write: Once in normal and emulation modes, anytime in special modes
NOTE
Writes to this register take one cycle to go into effect.
This register initializes the position of the internal RAM within the on-chip system memory map.
Table 3-1. INITRM Field Descriptions
Field
Description
7:3
Internal RAM Map Position — These bits determine the upper five bits of the base address for the system’s
RAM[15:11] internal RAM array.
0
RAMHAL
RAM High-Align — RAMHAL specifies the alignment of the internal RAM array.
0 Aligns the RAM to the lowest address (0x0000) of the mappable space
1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
MC3S12RG128 Data Sheet, Rev. 1.05
116
Freescale Semiconductor