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MC3S12RG128 Datasheet, PDF (81/546 Pages) Freescale Semiconductor, Inc – Microcontrollers
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.1.3 Port T Data Direction Register (DDRT)
Module Base + 0x_0002
R
W
Reset
7
DDRT7
0
6
DDRT6
0
5
DDRT5
0
4
DDRT4
0
3
DDRT3
0
2
DDRT2
0
1
DDRT1
0
0
DDRT0
0
Figure 2-5. Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
• The ECT forces the I/O state to be an output for each timer port associated with an enabled output
compare. In these cases the data direction bits will not change.
• The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output
compare is disabled.
• The timer input capture always monitors the state of the pin.
Table 2-3. DDRT Field Descriptions
Field
Description
7–0
DDRT[7:0]
Data Direction Port T Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on
PTT or PTIT registers, when changing the DDRT register.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
81