MC3S12RG128 Datasheet, PDF (453/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3.2.6 SCI Data Registers (SCIDRH and SCIDRL)
Module Base + 0x_0006
7
6
5
4
3
2
1
0
R
R8
0
0
0
0
0
0
T8
W
Reset
0
0
0
0
0
0
0
0
Module Base + 0x_0007
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-8. SCI Data Registers (SCIDRH and SCIDRL)
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 16-7. SCIDRH AND SCIDRL Field Descriptions
Field
7
R8
6
T8
7–0
R[7:0]
T[7:0]
Description
Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
Received Bits — Received bits seven through zero for 9-bit or 8-bit data formats
Transmit Bits — Transmit bits seven through zero for 9-bit or 8-bit formats
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH), then SCIDRL.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
453