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MC3S12RG128 Datasheet, PDF (120/546 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.6 Memory Size Register 0 (MEMSIZ0)
Module Base + 0x001C
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
R REG_SW0
0
EEP_SW1 EEP_SW0
0
RAM_SW2
W
Reset
â
â
â
â
â
â
= Unimplemented or Reserved
Figure 3-8. Memory Size Register 0 (MEMSIZ0)
1
RAM_SW1
â
0
RAM_SW0
â
Read: Anytime
Write: Writes have no effect
Reset: Deï¬ned at chip integration, see device overview section.
The MEMSIZ0 register reï¬ects the state of the register, EEPROM and RAM memory space conï¬guration
switches at the core boundary which are conï¬gured at system integration. This register allows read
visibility to the state of these switches.
Table 3-5. MEMSIZ0 Field Descriptions
Field
Description
7
REG_SW0
Allocated System Register Space
0 Allocated system register space size is 1K byte
1 Allocated system register space size is 2K byte
5:4
Allocated System EEPROM Memory Space â The allocated system EEPROM memory space size is as
EEP_SW[1:0] given in Table 3-6.
2
Allocated System RAM Memory Space â The allocated system RAM memory space size is as given in
RAM_SW[2:0] Table 3-7.
Table 3-6. Allocated EEPROM Memory Space
eep_sw1:eep_sw0
00
01
10
11
Allocated EEPROM Space
0K byte
2K bytes
4K bytes
8K bytes
ram_sw2:ram_sw0
000
001
010
Table 3-7. Allocated RAM Memory Space
Allocated
RAM Space
2K bytes
4K bytes
6K bytes
RAM
Mappable Region
2K bytes
4K bytes
8K bytes2
INITRM
Bits Used
RAM[15:11]
RAM[15:12]
RAM[15:13]
RAM Reset
Base Address1
0x0800
0x0000
0x0800
MC3S12RG128 Data Sheet, Rev. 1.05
120
Freescale Semiconductor
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