MC3S12RG128 Datasheet, PDF (314/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.4.1 Enhanced Capture Timer Modes of Operation
The Enhanced Capture Timer has eight Input Capture, Output Compare (IC/OC) channels same as on the
HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by
selecting the IOSn bit in TIOS register, they are called Input Capture (IC) channels.
Four IC channels are the same as on the standard timer with one capture register each which memorizes
the timer value captured by an action on the associated input pin.
Four other IC channels, in addition to the capture register, have also one buffer each called holding register.
This permits to memorize two different timer values without generation of any interrupt.
Four 8-bit pulse accumulators are associated with the four buffered IC channels. Each pulse accumulator
has a holding register to memorize their value by an action on its external input. Each pair of pulse
accumulators can be used as a 16-bit pulse accumulator.
The 16-bit modulus down-counter can control the transfer of the IC registers contents and the pulse
accumulators to the respective holding registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.
10.4.1.1 IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels.
An IC register is empty when it has been read or latched into the holding register.
A holding register is empty when it has been read.
10.4.1.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding
NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC
register are overwritten by the new value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless
it is empty. This will prevent the captured value to be overwritten until it is read.
10.4.1.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels.
1. IC Latch Mode:
When enabled (LATQ = 1), the main timer value is memorized in the IC register by a valid
input pin transition. See Figure 10-37.
The value of the buffered IC register is latched to its holding register by the Modulus counter
for a given period when the count reaches zero, by a write 0x0000 to the modulus counter or
by a write to ICLAT in the MCCTL register.
If the corresponding NOVWn bit of the ICOVW register is cleared, with a new occurrence of
a capture, the contents of IC register are overwritten by the new value. In case of latching, the
contents of its holding register are overwritten.
MC3S12RG128 Data Sheet, Rev. 1.05
314
Freescale Semiconductor