MC3S12RG128 Datasheet, PDF (316/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
accepted, depending on their relative alignment with the sample points.
4. Input pulses with a duration of DLY_CNT or longer are accepted.
10.4.1.2 Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC
buffered channels. A pulse accumulator counts the number of active edges at the input of its channel.
The user can prevent 8-bit pulse accumulators counting further than 0x00FF by PACMX control bit in
ICSYS (0x002B). In this case a value of 0x00FF means that 255 counts or more have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. See Figure 10-40. There are
two modes of operation for the pulse accumulators.
10.4.1.2.1 Pulse Accumulator Latch Mode
The value of the pulse accumulator is transferred to its holding register when the modulus down-counter
reaches zero, a write 0x0000 to the modulus counter or when the force latch control bit ICLAT is written.
At the same time the pulse accumulator is cleared.
10.4.1.2.2 Pulse Accumulator Queue Mode
When queue mode is enabled, reads of an input capture holding register will transfer the contents of the
associated pulse accumulator to its holding register.
At the same time the pulse accumulator is cleared.
10.4.1.3 Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used
to latch the values of the IC registers and the pulse accumulators to their holding registers.
The action of latching can be programmed to be periodic or only once.
10.4.1.4 Channel Configurations
Timer Channels can be configured as input capture channels or output compare channels. Following are
the ways a port can be configured as an output for OC.
The pin associated with channel 7 becomes output-tied to OC7 when
• TEN = 1, IOS7 = 1, and either or both of OM7 and OL7 are set. or
• OC7M7 =1 and IOS7 = 1.
When masking, the timer does not have to be enabled so that the pin associated with OCn becomes an
output tied to OCn.
MC3S12RG128 Data Sheet, Rev. 1.05
316
Freescale Semiconductor