MC3S12RG128 Datasheet, PDF (220/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Register
Name
0x001D
ATDDR6L
0x001E
ATDD47H
0x001F
ATDD47L
Bit 7
6
5
4
3
2
10-BIT BIT 7
8-BIT BIT 7 MSB
W
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
10-BIT
0
0
0
0
0
0
8-BIT
0
0
0
0
0
0
W
10-BIT BIT 7
BIT 7 MSB
8-BIT
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 5 of 5)
1
BIT 1
BIT 1
BIT 9 MSB
0
BIT 1
BIT 1
Bit 0
BIT 0
BIT 0
BIT 8
0
BIT 0
BIT 0
8.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0000
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
0
WRAP2
0
1
Figure 8-3. ATD Control Register 0 (ATDCTL0)
1
WRAP1
1
0
WRAP0
1
Read: Anytime
Write: Anytime
Table 8-1. ATDCTL0 Field Descriptions
Field
Description
2–0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[2:0] multi-channel conversions. The coding is summarized in Table 8-2.
WRAP2
0
0
0
0
1
1
Table 8-2. Multi-Channel Wrap Around Coding
WRAP1
0
0
1
1
0
0
WRAP0
0
1
0
1
0
1
Multiple Channel Conversions (MULT = 1)
Wrap Around to AN0 after Converting
Reserved
AN1
AN2
AN3
AN4
AN5
MC3S12RG128 Data Sheet, Rev. 1.05
220
Freescale Semiconductor