MC3S12RG128 Datasheet, PDF (304/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-25. ICSYS Field Descriptions (continued)
Field
3
TFMOD
2
PACMX
1
BUFFEN
0
LAT!
Description
Timer Flag-setting Mode — Use of the TFMOD bit in the ICSYS register (0x002B) in conjunction with the use
of the ICOVW register (0x002A) allows a timer interrupt to be generated after capturing two values in the capture
and holding registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the corresponding capture and holding registers
are emptied, an input capture event will first update the related input capture register with the main timer
contents. At the next event the TCn data is transferred to the TCnH register, The TCn is updated and the CnF
interrupt flag is set.
In all other input capture cases the interrupt flag is set by a valid external event on PTn.
0 The timer flags C3F–C0F in TFLG1 (0x000E) are set when a valid input capture transition on the
corresponding port pin occurs.
1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 (0x000E) are set only when
a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags
C3F–C0F are set the same way as for TFMOD = 0.
8-Bit Pulse Accumulators Maximum Count
0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,
it will be incremented to 0x0000.
1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value
0x00FF indicates a count of 255 or more.
IC Buffer Enable
0 Input Capture and pulse accumulator holding registers are disabled.
1 Input Capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ
control bit. Write one into ICLAT bit in MCCTL (0x0026), when LATQ is set will produce latching of input
capture and pulse accumulators registers into their holding registers.
Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC
and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled.
Write one into ICLAT bit in MCCTL (0x0026), when LATQ and BUFEN are set will produce latching of input
capture and pulse accumulators registers into their holding registers.
0 Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input
pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding
register and the IC register memorizes the new timer value.
1 Latch Mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is
written into the count register MCCNT (seeSection 10.4.1.1.2, “Buffered IC Channels”). With a latching event
the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse
accumulators are cleared.
MC3S12RG128 Data Sheet, Rev. 1.05
304
Freescale Semiconductor