MC3S12RG128 Datasheet, PDF (526/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
4 _{XCLKS =0 during reset}
A.6.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.6.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve good filter characteristics.
C_p
VDDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
∆
K_Φ
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure A-3. Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K₁, f₁ and i_ch from Table A-18.
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o--}₌^-) _{–100 ⋅ e}^{(---6---–0---1-–--0---50---0---}₌⁾ _-90.48MHz/V
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
i_ch is the current in tracking mode.
= 316.7Hz/Ω
MC3S12RG128 Data Sheet, Rev. 1.05
526
Freescale Semiconductor