MC3S12RG128 Datasheet, PDF (532/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
2
SCK
(CPOL = 1)
(INPUT) ¹⁰
7
MISO
see
(OUTPUT)
note
1
4
SLAVE MSB
MOSI
(INPUT)
5
6
MSB IN
NOTE: Not defined!
12
4
12
9
BIT 6 . . . 1
BIT 6 . . . 1
13 3
13
11
11
SLAVE LSB OUT
8
SEE
NOTE
LSB IN
Figure A-8. SPI Slave Timing (CPHA=0)
In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
2
12
4
4
12
9
see
note
SLAVE
MSB OUT
7
5
6
MSB IN
11
BIT 6 . . . 1
BIT 6 . . . 1
3
13
13
8
SLAVE LSB OUT
LSB IN
NOTE: Not defined!
Figure A-9. SPI Slave Timing (CPHA=1)
In Table A-22 the timing characteristics for slave mode are listed.
MC3S12RG128 Data Sheet, Rev. 1.05
532
Freescale Semiconductor