MC3S12RG128 Datasheet, PDF (292/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
R
C7F
W
6
C6F
5
C5F
4
C4F
3
C3F
2
C2F
1
C1F
0
C0F
Reset
0
0
0
0
0
0
0
0
Figure 10-14. Main Timer Interrupt Flag 1 (TFLG1)
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one to
the bit. Use of the TFMOD bit in the ICSYS register (0x002B) in conjunction with the use of the ICOVW
register (0x002A) allows a timer interrupt to be generated after capturing two values in the capture and
holding registers instead of generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared).
Writing a zero will not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010–0x001F) will cause the corresponding channel flag CnF to be cleared.
Table 10-12. TFLG1 Field Descriptions
Field
7–0
C[7:0]F
Description
Input Capture/Output Compare Channel “n” Flag — C0F can also be set by 16-bit Pulse Accumulator B
(PACB). C3F–C0F can also be set by 8 - bit pulse accumulators PAC3–PAC0.
10.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-15. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one.
Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 10-13. TFLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. See also TCRE control bit explanation found in
Section 10.3.2.11, “Timer System Control Register 2 (TSCR2)”.
MC3S12RG128 Data Sheet, Rev. 1.05
292
Freescale Semiconductor