MC3S12RG128 Datasheet, PDF (306/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.26 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
PBOVF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-30. Pulse Accumulator B Flag Register (PBFLG)
Read or write anytime.
Table 10-27. PBFLG Field Descriptions
Field
1
PBOVF
Description
Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from
0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register when TFFCA bit in
register TSCR(0x0006) is set.
When PACMX = 1, PBOVF bit can also be set if 8 - bit pulse accumulator 1 (PAC1) reaches 0x00FF and followed
an active edge comes on PT1.
MC3S12RG128 Data Sheet, Rev. 1.05
306
Freescale Semiconductor