MC3S12RG128 Datasheet, PDF (137/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Name
0x000D
RDRIV
0x000E
EBICTL
0x000F
Reserved
0x001E
IRQCR
0x0032
PORTK
0x0033
DDRK
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Bit 7
6
5
4
3
2
R
0
0
0
0
RDPK
RDPE
W
R
0
0
0
0
0
0
W
R
0
0
0
0
0
0
W
R
0
0
0
0
IRQE
IRQEN
W
R
Bit 7
6
5
4
3
2
W
R
Bit 7
6
5
4
3
2
W
= Unimplemented or Reserved
Figure 4-2. MEBI Register Summary (continued)
1
RDPB
0
0
Bit 0
RDPA
ESTR
0
0
0
1
Bit 0
1
Bit 0
4.3.2 Register Descriptions
4.3.2.1 Port A Data Register (PORTA)
Module Base + 0x0000
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
R
Bit 7
6
5
4
3
2
1
W
Reset
0
0
0
0
0
0
0
Single Chip PA7
PA6
PA5
PA4
PA3
PA2
PA1
Expanded Wide,
Emulation Narrow with AB/DB15
IVIS, and Peripheral
AB/DB14
AB/DB13
AB/DB12
AB/DB11
AB/DB10
AB/DB9
Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and AB9 and
DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2 DB9/DB1
Figure 4-3. Port A Data Register (PORTA)
0
Bit 0
0
PA0
AB/DB8
AB8 and
DB8/DB0
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
137