MC3S12RG128 Datasheet, PDF (293/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.14 Timer Input Capture/Output Compare Registers (TC0–TC7)
Module Base + 0x0010–0x0011
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0 tc0
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x0012–0x0013
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1 tc1
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x0014–0x0015
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2 tc2
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x0016–0x0017
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3 tc3
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x0018–0x0019
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x001A–0x001B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5 tc5
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x001C–0x001D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x001E–0x001F
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7
W 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-16. Timer Input Capture/Output Compare Registers (TC0–TC7)
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
293