MC3S12RG128 Datasheet, PDF (530/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Table A-20. Measurement Conditions
Description
Value
Unit
Drive mode
full drive mode
—
Load capacitance C_LOAD,
50
pF
on all outputs
Thresholds for delay
(20% / 80%) V_DDX
V
measurement points
A.8.1 Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
2
1
12
4
4
12
13
3
13
5
6
MISO
(INPUT)
MSB IN²
BIT 6 . . . 1
LSB IN
MOSI
(OUTPUT)
10
MSB OUT²
9
BIT 6 . . . 1
11
LSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6. SPI Master Timing (CPHA=0)
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
MC3S12RG128 Data Sheet, Rev. 1.05
530
Freescale Semiconductor