MC3S12RG128 Datasheet, PDF (291/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
TOI
TCRE
PR2
PR1
PR0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-13. Timer System Control Register 2 (TSCR2)
Read or write anytime.
Table 10-10. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
2–0
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited
1 Hardware interrupt requested when TOF flag set
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs
1 Counter reset by a successful output compare 7
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select — These three bits specify the number of ÷2 stages that are to be inserted between the
bus clock and the main timer counter. See Table 10-11.
Note: The newly selected prescale factor will not take effect until the next synchronized edge where all prescale
counter stages equal zero.
Table 10-11. Prescaler Selection
PR2
PR1
PR0
Prescale Factor
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
291