MC3S12RG128 Datasheet, PDF (142/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.5 Reserved Registers
Module Base + 0x0004
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. Reserved Register
Module Base + 0x0005
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-8. Reserved Register
Module Base + 0x0006
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. Reserved Register
Module Base + 0x0007
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-10. Reserved Register
MC3S12RG128 Data Sheet, Rev. 1.05
142
Freescale Semiconductor