MC3S12RG128 Datasheet, PDF (255/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.10
Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the CRG’s functionality.
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-13. Reserved Register (FORBYP)
Read: always read 0x0000 except in special modes
Write: only in special modes
9.3.1.11
Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the CRG’s functionality.
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-14. Reserved Register (CTCTL)
Read: always read 0x0080 except in special modes
Write: only in special modes
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
255