MC3S12RG128 Datasheet, PDF (23/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
1.1.4 Device Memory Map
Table 1-1 shows the device register memory map of the MC3S12RG128 after reset. Note that after reset
the bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.
Table 1-1. Device Memory Map
Address
Module
Size
(Bytes)
0x0000–0x0017
0x0018
0x0019
0x001A–0x001B
0x001C–0x001F
0x0020–0x0027
0x0028–0x002F
0x0030–0x0033
0x0034–0x003F
0x0040–0x007F
0x0080–0x009F
0x00A0–0x00C7
0x00C8–0x00CF
0x00D0–0x00D7
0x00D8–0x00DF
0x00E0–0x00E7
0x00E8–0x00EF
0x00F0–0x00F7
0x00F8–0x00FF
0x0100–0x010F
0x0110–0x011B
0x011C–0x011F
0x0120–0x013F
0x0140–0x017F
0x0180–0x01BF
0x01C0–0x01FF
0x0200–0x023F
0x0240–0x027F
0x0280–0x02BF
0x02C0–0x02FF
0x0300–0x035F
0x0360–0x03FF
0x0000–0x1FFF
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Voltage Regulator (VREG3V3)
Device ID register (PARTID)
CORE (MEMSIZ, IRQ, HPRIO)
Reserved
CORE (Background Debug Module)
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Enhanced Capture Timer 16-bit 8 channels
Analog to Digital Converter 10-bit 8 channels (ATD0)
Pulse Width Modulator 8-bit 8 channels (PWM)
Serial Communications Interface (SCI0)
Serial Communications Interface (SCI1)
Serial Peripheral Interface (SPI0)
Inter IC Bus
Reserved
Serial Peripheral Interface (SPI1)
Reserved
ROM Control/Status Registers
Reserved
Reserved
Analog to Digital Converter 10-bit 8 channels (ATD1)
Freescale Scalable CAN (CAN0)
Reserved
Reserved
Reserved
Port Integration Module (PIM)
Freescale Scalable CAN (CAN4)
Reserved
Reserved
Reserved
RAM array
24
1
1
2
4
8
8
4
12
64
32
40
8
8
8
8
8
8
8
16
12
4
32
64
64
64
64
64
64
64
96
160
8192
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
23