MC3S12RG128 Datasheet, PDF (79/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2 Register Descriptions
Table 2-2 summarizes the effect on the various configuration bits, data direction (DDR), output level (I/O),
reduced drive (RDR), pull enable (PE), pull select (PS) and interrupt enable (IE) for the ports. The
configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Table 2-2. Pin Configuration Summary
DDR IO RDR PE
PS
IE¹
Function
0
X
X
0
X
0
X
X
1
0
0
X
X
1
1
0
X
X
0
0
0
X
X
0
1
0
X
X
1
0
0
X
X
1
1
1
0
0
X
X
1
1
0
X
X
1
0
1
X
X
1
1
1
X
X
1
0
0
X
0
1
1
0
X
1
1
0
1
X
0
1
1
1
X
1
1 _{Applicable only on port P, H and J.}
0
Input
0
Input
0
Input
1
Input
1
Input
1
Input
1
Input
0
Output, full drive to 0
0
Output, full drive to 1
0
Output, reduced drive to 0
0
Output, reduced drive to 1
1
Output, full drive to 0
1
Output, full drive to 1
1
Output, reduced drive to 0
1
Output, reduced drive to 1
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
79