HD64F2357F20V Datasheet, PDF (970/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
H'FFB2
H'FFB3
8-Bit Timer Channel 0
8-Bit Timer Channel 1
TCSR0 Bit
:7
6
5
4
3
2
1
0
CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W
TCSR1 Bit
:7
6
5
4
CMFB CMFA OVF
—
Initial value : 0
0
0
1
Read/Write : ^{R/(W)* R/(W)* R/(W)* —}
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Output Select
0 0 No change when compare
match A occurs
1 0 is output when compare
match A occurs
1 0 1 is output when compare
match A occurs
1 Output is inverted when
compare match A
occurs (toggle output)
Output Select
0 0 No change when compare match B occurs
1 0 is output when compare match B occurs
1 0 1 is output when compare match B occurs
1 Output is inverted when compare match B
occurs (toggle output)
A/D Trigger Enable (TCSR0 only)
0 A/D converter start requests by compare match A are disabled
1 A/D converter start requests by compare match A are enabled
Timer Overflow Flag
0 [Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
1 [Setting condition]
Set when TCNT overflows (changes from H'FF to H'00)
Compare Match Flag A
0 [Clearing conditions]
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0.
1 [Setting condition]
Set when TCNT matches TCORA
Compare Match Flag B
0 [Clearing conditions]
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0.
1 [Setting condition]
Set when TCNT matches TCORB
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.6.00 Oct.28.2004 page 940 of 1016
REJ09B0138-0600H