HD64F2357F20V Datasheet, PDF (540/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

In serial reception, the SCI operates as described below.
[1] The SCI performs internal initialization in synchronization with serial clock input or output.
[2] The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in
the error check, the operation is as shown in table 14-11.
Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the
error check.
[3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is
generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is
generated.
Figure 14-19 shows an example of SCI operation in reception.
Serial
clock
Serial
data
RDRF
ORER
Bit 7 Bit 0
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt service
routine
1 frame
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
Figure 14-19 Example of SCI Operation in Reception
Rev.6.00 Oct.28.2004 page 510 of 1016
REJ09B0138-0600H