HD64F2357F20V Datasheet, PDF (181/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.7.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the
AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected
for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is
designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to
1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6-30 (a) and (b). The timing shown in figure 6-30 (a) is
for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6-30 (b) is for the case where both these
bits are cleared to 0.
Full access
Burst access
T₁
T₂
T₃
T₁
T₂
T₁
T₂
ø
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
Rev.6.00 Oct.28.2004 page 151 of 1016
REJ09B0138-0600H