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HD64F2357F20V Datasheet, PDF (548/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series
15.1.2 Block Diagram
Figure 15-1 shows a block diagram of the Smart Card interface.
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
SCMR
BRR
SSR
TSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
Parity generation
Clock
Parity check
Legend:
SCMR: Smart Card mode register
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
ø
ø/4
ø/16
ø/64
TXI
RXI
ERI
Figure 15-1 Block Diagram of Smart Card Interface
15.1.3 Pin Configuration
Table 15-1 shows the Smart Card interface pin configuration.
Table 15-1 Smart Card Interface Pins
Channel
0
1
2
Pin Name
Serial clock pin 0
Receive data pin 0
Transmit data pin 0
Serial clock pin 1
Receive data pin 1
Transmit data pin 1
Serial clock pin 2
Receive data pin 2
Transmit data pin 2
Symbol
SCK0
RxD0
TxD0
SCK1
RxD1
TxD1
SCK2
RxD2
TxD2
I/O
I/O
Input
Output
I/O
Input
Output
I/O
Input
Output
Function
SCI0 clock input/output
SCI0 receive data input
SCI0 transmit data output
SCI1 clock input/output
SCI1 receive data input
SCI1 transmit data output
SCI2 clock input/output
SCI2 receive data input
SCI2 transmit data output
Rev.6.00 Oct.28.2004 page 518 of 1016
REJ09B0138-0600H