HD64F2357F20V Datasheet, PDF (230/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and
when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt
request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI
transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A
interrupts. External requests can be set for channel B only.
When the DMAC is used in single address mode, only channel B can be set.
Figure 7-6 shows an example of the setting procedure for idle mode.
Idle mode setting
Set DMABCRH
[1]
Set transfer source
and transfer destination [2]
addresses
Set number of transfers [3]
Set DMACR
[4]
Read DMABCRL
[5]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Set DMABCRL
[6]
Idle mode
Figure 7-6 Example of Idle Mode Setting Procedure
Rev.6.00 Oct.28.2004 page 200 of 1016
REJ09B0138-0600H