HD64F2357F20V Datasheet, PDF (179/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

T_Rp
T_Rcr
ø
Software
standby
T_Rc3
CSn, (RAS)
CAS, LCAS
HWR, (WE)
High
Note: n = 2 to 5
Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0)
6.6 DMAC Single Address Mode and DRAM Interface
When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When
DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed
is selected.
6.6.1 When DDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low
from the T_C1 state in the case of the DRAM interface.
Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1.
T_p
T_r
T_c1
T_c2
ø
A₂₃ to A₀
Row
Column
CSn, (RAS)
CAS, (UCAS),
LCAS, (LCAS)
Read
HWR, (WE)
D₁₅ to D₀
Write
HWR, (WE)
D₁₅ to D₀
DACK
Note: n = 2 to 5
Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)
Rev.6.00 Oct.28.2004 page 149 of 1016
REJ09B0138-0600H