HD64F2357F20V Datasheet, PDF (191/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.10.4 Transition Timing
Figure 6-37 shows the timing for transition to the bus-released state.
ø
Address bus
Data bus
AS
RD
HWR, LWR
CPU cycle
T₀
T₁
T₂
Address
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
CPU
cycle
BREQ
BACK
BREQO^*
Minimum
1 state
[1]
[2]
[3]
[4]
[5]
[6]
[1]
Low level of BREQ pin is sampled at rise of T₂ state.
[2]
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
[3]
BREQ pin state is still sampled in external bus released state.
[4]
High level of BREQ pin is sampled.
[5]
BACK pin is driven high, ending bus release cycle.
[6]
BREQO signal goes high 1.5 clocks after BACK signal goes high.
Note: * Output only when BREQOE is set to 1.
Figure 6-37 Bus-Released State Transition Timing
6.10.5 Usage Note
When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts.
Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep
mode.
Rev.6.00 Oct.28.2004 page 161 of 1016
REJ09B0138-0600H