HD64F2357F20V Datasheet, PDF (338/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

9.9.2 Register Configuration (On-Chip ROM Version Only)
Table 9-15 shows the port B register configuration.
Table 9-15 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note: * Lower 16 bits of the address.
Abbreviation R/W
PBDDR
W
PBDR
R/W
PORTB
R
PBPCR
R/W
Initial Value
H'00
H'00
Undefined
H'00
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71
Port B Data Direction Register (PBDDR) (On-Chip ROM Version Only)
Bit
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR
cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Mode 6
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the
pin an input port.
• Modes 4 and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Port B Data Register (PBDR) (On-Chip ROM Version Only)
Bit
:
Initial value :
R/W
:
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB₇ to PB₀). PBDR is initialized to
H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software
standby mode.
Rev.6.00 Oct.28.2004 page 308 of 1016
REJ09B0138-0600H