HD64F2357F20V Datasheet, PDF (668/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

19.18 Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU.
There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory
programming/erasing (the programming control program) should be located and executed in on-chip RAM or external
memory. When the program is located in external memory, an instruction for programming the flash memory and the
following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the
instruction for programming the flash memory is executed.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is
executed by a program in flash memory.
2. Perform programming in the erased state. Do not perform additional programming on previously programmed
addresses.
19.18.1 Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 19-48 to write data or programs to flash
memory. Performing program operations according to this flowchart will enable data or programs to be written to flash
memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be
carried out 128 bytes at a time.
For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register 1
(FLMCR1) and the maximum number of programming operations (N), see section 22.3.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-
byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data
area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80.
128 consecutive byte data transfers are performed. The program address and program data are latched in the flash
memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be
written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than
(y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out
by setting the PSU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program
mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set
the programming time according to the table in the programming flowchart in figure 19-48.
19.18.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the
flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then
the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and
the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-
verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units),
the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation.
Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19-48) and
transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode in FLMCR1
to 0, and wait again for at least (θ) µs. If reprogramming is necessary, set program mode again, and repeat the
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