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HD64F2357F20V Datasheet, PDF (764/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series
22.6.3 AC Characteristics
Figure 22-67 show, the test conditions for the AC characteristics.
LSI output pin
5V
RL
C
RH
C = 90 pF: Ports 1, A to F
C = 30 pF: Ports 2, 3, 5, 6, G
RL = 2.4 kΩ
RH = 12 kΩ
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V
Figure 22-67 Output Load Circuit
(1) Clock Timing
Table 22-26 lists the clock timing
Table 22-26 Clock Timing
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Item
Condition A Condition B Condition C
Test
Symbol Min Max Min Max Min Max Unit Conditions
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator setting
time at reset (crystal)
t cyc
t CH
t CL
t Cr
t Cf
t OSC1
100 500 50
35 — 20
35 — 20
— 15 —
— 15 —
20 — 10
500 76
— 23
— 23
5—
5—
— 20
500 ns Figure 22-68
— ns
— ns
15 ns
15 ns
— ms Figure 22-69
Clock oscillator setting time t OSC2
in software standby (crystal)
20 — 10 — 20 — ms Figure 21-2
External clock output
stabilization delay time
t DEXT
500 — 500 — 500 — µs Figure 22-69
Rev.6.00 Oct.28.2004 page 734 of 1016
REJ09B0138-0600H