HD64F2357F20V Datasheet, PDF (626/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

19.9.3 Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify
flowchart (single-block erase) shown in figure 19-20.
The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1,
FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash
Memory Characteristics.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or
2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the
watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß)
µs as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in
FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in
FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not
exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary
before starting the erase procedure.
19.9.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR2
is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating
mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ)
µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address
is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased
(all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased,
set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for
at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0. If there are any
unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-
verify sequence in the same way.
Rev.6.00 Oct.28.2004 page 596 of 1016
REJ09B0138-0600H