HD64F2357F20V Datasheet, PDF (1043/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Appendix F Timing of Transition to and Recovery from Hardware
Standby Mode
F.1 Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 system clock
cycles before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay
from STBY low to RES high: 0 ns or more).
STBY
RES
t₁≥10 t_cyc
t₂≥0 ns
Figure F-1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained,
RES does not have to be driven low as in (1).
F.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a
power-on reset.
STBY
RES
NMI
t≥100 ns
t_OSC
t_NMIRH
Figure F-2 Timing of Recovery from Hardware Standby Mode
Rev.6.00 Oct.28.2004 page 1013 of 1016
REJ09B0138-0600H