HD64F2357F20V Datasheet, PDF (740/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

(3) Bus Timing
Table 22-16 lists the bus timing.
Table 22-16 Bus Timing
Conditions:
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø= 10 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Address delay time
Address setup time
Symbol
t _AD
t _AS
Address hold time
t _AH
Precharge time
t _PCH
CS delay time 1
CS delay time 2
CS delay time 3
AS delay time
RD delay time 1
RD delay time 2
CAS delay time
Read data setup time
Read data hold time
Read data access time 1
t _CSD1
t _CSD2
t _CSD3
t _ASD
t _RSD1
t _RSD2
t _CASD
t _RDS
t _RDH
t _ACC1
Read data access time 2 t _ACC2
Read data access time 3 t _ACC3
Read data access
time 4
Read data access
time 5
WR delay time 1
WR delay time 2
WR pulse width 1
t _ACC4
t _ACC5
t _WRD1
t _WRD2
t _WSW1
WR pulse width 2
t _WSW2
Write data delay time
Write data setup time
t _WDD
t _WDS
Write data hold time
t _WDH
WR setup time
t _WCS
Min
—
0.5 ×
t _cyc – 15
0.5 ×
t _cyc – 10
1.5 ×
t _cyc – 20
—
—
—
—
—
—
—
15
0
—
—
—
—
—
—
—
1.0 ×
t _cyc – 20
1.5 ×
t _cyc – 20
—
0.5 ×
t _cyc – 20
0.5 ×
t _cyc – 10
0.5 ×
t _cyc – 10
Condition
Max
20
—
—
—
20
20
25
20
20
20
20
—
—
1.0 ×
t _cyc – 25
1.5 ×
t _cyc – 25
2.0 ×
t _cyc – 25
2.5 ×
t _cyc – 25
3.0 ×
t _cyc – 25
20
20
—
—
30
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Figure 22-40 to
Figure 22-47
Rev.6.00 Oct.28.2004 page 710 of 1016
REJ09B0138-0600H