HD64F2357F20V Datasheet, PDF (750/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

(5) Timing of On-Chip Supporting Modules
Table 22-18 lists the timing of on-chip supporting modules.
Table 22-18 Timing of On-Chip Supporting Modules
Conditions:
V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 10 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Symbol
PORT Output data delay time t _PWD
Input data setup time t _PRS
Input data hold time t _PRH
PPG Pulse output delay time t _POD
TPU Timer output delay time t _TOCD
Timer input setup time t _TICS
Timer clock input setup t _TCKS
time
Timer clock Single
pulse width edge
t _TCKWH
Both
edges
t _TCKWL
TMR
Timer output delay time t_TMOD
Timer reset input setup t_TMRS
time
Timer clock input setup t_TMCS
time
Timer clock
pulse width
Single
edge
Both
edges
t _TMCWH
t _TMCWL
SCI Input clock Asynchro- t _Scyc
cycle
nous
Synchro-
nous
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay
time
t _SCKW
t _SCKr
t _SCKf
t _TXD
Receive data setup
t _RXS
time (synchronous)
Receive data hold
t _RXH
time (synchronous)
A/D Trigger input setup
con- time
verter
t _TRGS
Condition
Min
Max
—
50
30
—
30
—
—
50
—
50
30
—
30
—
1.5
—
2.5
—
—
50
30
—
30
—
1.5
—
2.5
—
4
—
6
—
0.4
0.6
—
1.5
—
1.5
—
50
50
—
50
—
30
—
Unit
ns
ns
ns
ns
t _cyc
ns
ns
ns
t _cyc
t _cyc
t _Scyc
t _cyc
ns
ns
ns
ns
Test
Conditions
Figure 22-54
Figure 22-55
Figure 22-56
Figure 22-57
Figure 22-58
Figure 22-60
Figure 22-59
Figure 22-61
Figure 22-62
Figure 22-63
Rev.6.00 Oct.28.2004 page 720 of 1016
REJ09B0138-0600H